1. Field
Various exemplary embodiments of the present invention relate to a semiconductor design technique, and more particularly, to a semiconductor device that detects and corrects data errors and an operating method thereof.
2. Description of the Related Art
A memory device, such as, e.g., a Dynamic Random-Access Memory (DRAM), may include a plurality of memory cells that are arrayed in the form of a matrix. As the capacity of memory devices increases and the dimension of fabricated memory devices shrinks, the number of defective memory cells among the memory cells increases as well. In general, defective memory cells may include failed memory cells and weak memory cells. The failed memory cells may be defined as memory cells that do not function in terms of hardware. For example, the failed memory cells may be defined as the memory cells that do not operate due to a defect occurring during the semiconductor fabrication process, such as a memory cell of which the connection line is short-circuited. The weak memory cells may be defined as memory cells that do not function in terms of software. For example, the weak memory cells may include a memory cell of which the data retention time does not reach a reference time.
In recent times, data retention characteristics of a memory cell tend to decrease due to the trend of low-voltage high-speed operation and shrinking fabrication dimensions that may also lead to an increase in the number of weak memory cells. In other words, the frequency that error bits intermittently occur in the data stored in a DRAM is increasing drastically. To solve the problem, there is an effort for detecting and correcting the error bits through an Error Correction Code (ECC) operation inside of the DRAM.
Meanwhile, as the degree of integration of a memory device increases, the space between a plurality of word lines included in the memory device is reduced, and the coupling effect between adjacent word lines increases. As a result, if a specific word line is activated too often or frequently, the data of memory cells coupled to a word line adjacent to the specific word line may be corrupted.
When a specific word line is repeatedly activated in a time threshold value, that is, when the specific word line is hammered or a row hammer event occurs, data of memory cells electrically coupled to word lines, which are physically adjacent to the specific word line, may be affected. A leakage current and a parasitic current caused by repeated access to a specific word line may drift data corresponding to non-accessed word lines physically adjacent to the specific word line. Such drift, influence and the like of the data between word lines are herein referred to as a row disturbance phenomenon.
Particularly, when error bits that can be detected and corrected through the ECC operation meet the condition for the row hammer event, the error bits increase and consequently, there is a high possibility that the error bits become uncorrectable error bits. Although a memory device can reduce the influence of memory cells due to the hammered word line through a refresh operation, there is a limitation in increasing the frequency of the refresh operation for a specific word line in a system in which the refresh operation interval is short, such as a mobile device. Therefore, even in case of the error bits that can be detected and corrected through the ECC operation, it is desirable to develop a method for further increasing the reliability of data according to the refresh operation condition.